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Fuji Yang, Ph.D.
Fuji Yang, Ph.D.
AI & Informatics

He earned his Ph.D. from the École Nationale Supérieure des Télécommunications de Paris (ENST), France. Over his 30-year career in the semiconductor industry, he has worked at companies including Alcatel, Lucent Technologies, Agere Systems, and LSI Corporation. He contributed to and worked on various products including first zero-IF fully integrated RF transceiver for mobile phones, power management chips, optical communication transceivers, high-speed serial interfaces, ultra-low-power analog front-end circuits, and embedded memory IPs.

He has published several conference and journal papers including in ISSCC and JSSC, and holds 16 US patents.


  • Research Areas
    Analog and mixed-signal circuit designs, sensor interface circuits, AI algorithms and applications, neuromorphic computing.
  • Education
    1993
    Ph.D. in Microelectronics and Communications, École Nationale Supérieure des Télécommunications (ENST), Paris
    1988
    M.S. in Microwave and Optoelectronics, Université Pierre et Marie Curie (Paris VI), Paris
    1986
    B.S. in Electronic Science and Technology, East China Normal University
  • Work Experience
    2020-2024
    Principal Technical Staff, HFC Semiconductor Corp
    2017-2020
    Partner, Sinnocius LLC
    2015-2017
    Director of Analog and Mixed-Signal Circuit Design, ZTE TX
    2013-2015
    Senior Wireless RF Circuit Design Engineer, Blue Danube Systems
    2009-2013
    Principal engineer, Fresco Logic Corp
    1999-2009
    Distinguished Member of Technical Staff, Lucent Technologies, Agere Systems, and LSI Corp (through mergers)
    1996-1999
    RF and Baseband Circuit Design Engineer, Alcatel Mobile Communications
    1994-1996
    Postdoctoral Researcher, Department of Electrical Engineering, Swiss Federal Institute of Technology in Lausanne (EPFL)
  • Patents
    7,426,247 Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof.
    7,355,451 Common-mode shifting circuit for CML buffers.
    7,222,290 Method and apparatus for receiver detection on a PCI-Express bus.
    7,164,711Programmable receive-side channel equalizer.
    7,099,400 Multi-level pulse amplitude modulation receiver.
    6,586,977 Four quadrant analog mixer-based delay-locked loop for clock and data recovery.
    6,323,795 Electronic digital-to-analog converter circuit for a baseband transmission system.
    6,236,252 Low-noise current pulse generator device.
    6,161,000 Transmit-receive system and transmission method, in particular for a mobile telephone.
    EP1052772B1 (European Patent) A system and a method for producing a filtered signal having a given frequency and a radio transmitter transmitting at frequency set by a variable frequency oscillator.
    7.598.815 Multiple Frequency Generator for Quadrature Amplitude Modulated communications.
    7.577.225 Digital phase-locked loop.
    7.733.143Duty cycle correction circuit for high-speed clock signals.
    7.808.329Methods and apparatus for an improved phase linearity in a multi-phase based clock/timing recovery system.
  • Academic Achievements
    1. J. Chen, F.Saibi, E. Sackinger, J. Othmer, F. Yang, J. Lin, T. Huang, TP Liu, K. Azadet “A Multi-Carrier QAM Transceiver for Ultra-Wideband Optical Communication” IEEE Journal of Solid-State Circuits, vol 41, pp1876-1893, Aug 2006.
    2. J. Chen, F.Saibi, E. Sackinger, J. Othmer, F. Yang, J. Lin, T. Huang, TP Liu, K. Azadet “An integrated CMOS transceiver for a 40Gb/s SCM optical communication system” IEEE 2005 Custom Integrated Circuits Conference (CICC), pp135-138, San Jose, California, Sept. 18-21, 2005.
    3. J. Chen, G. Sheets, C. Guo, F. Saibi, F. Yang, K. Azadet “Electrical backplane equalization using programmable analog zeros and folded active inductors” 48th IEEE Midwest Symposium on Circuits and Systems, pp. 1366-1369, Cincinnati, Ohio, August 7-10, 2005.
    4. Yang F., O'Neill, J.H. Inglis, D., Othmer, J. “A CMOS Low-Power Multiple 2.5-3.125Gb/s Serial Link Macrocell for High IO Bandwidth Network ICs” IEEE Journal of Solid-State Circuits, Vol.37, No.12, Dec. 2002.
    5. F. Yang, J. O'Neill, P. Larsson “A 1.5V 86mW/ch 8-channel 622-3125Mb/s Serdes with selectable mux/demux ratio”, IEEE International Solid-State Circuits Conference (ISSCC) 2002, San Francisco, USA.
    6. F. Yang, C.C. Enz “A low distortion BiCMOS 7th-order Bessel filter operating at 2.5V”, IEEE Journal of Solid-State Circuits, vol.31, pp321-330, Mar. 1996.
    7. F. Yang, C.C. Enz “Design of low-power low voltage log-domain filter” IEEE International Symposium on Circuits & Systems(ISCAS) 1996, Atlanta, US.
    8. F. Yang, C.C. Enz “ A 2.5V low distortion 7th-order Bessel Filter” IEEE Custom Integrated Circuits Conference(CICC)1995, Santa Clara, US.
    9. F. Yang, C.C. Enz “A low-voltage low distortion BiCMOS OTA for CT filters” IEEE International Symposium on Circuits & Systems (ISCAS) 1995, Seattle, USA.
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