模拟与数模混合电路类设计。人体生理信息检测芯片、生化传感器阵列读出电路、智能感知的AI算法和神经形态计算等

微电子与通信专业博士，巴黎国立高等通讯学院

微波与光电子专业硕士，巴黎第六大学

电子科学技术专业学士，华东师范大学

HFC semiconductor Corp，主任技术专家

Sinnocius LLC，合伙人

ZTE TX，模拟与数模混合电路设计总监

Blue Danube Systems, 高级无线射频电路设计工程师

Fresco Logic Corp，主任工程师

朗讯技术公司、杰尔系统、LSI Corp (公司合并)，工程师、杰出工程师

阿尔卡特移动通信，射频与基带电路设计工程师

瑞士洛桑联邦理工学院电子工程系博后研究员

7,426,247 Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof.

7,355,451 Common-mode shifting circuit for CML buffers.

7,222,290 Method and apparatus for receiver detection on a PCI-Express bus.

7,164,711Programmable receive-side channel equalizer.

7,099,400 Multi-level pulse amplitude modulation receiver.

6,586,977 Four quadrant analog mixer-based delay-locked loop for clock and data recovery.

6,323,795 Electronic digital-to-analog converter circuit for a baseband transmission system.

6,236,252 Low-noise current pulse generator device.

6,161,000 Transmit-receive system and transmission method, in particular for a mobile telephone.

EP1052772B1 (European Patent) A system and a method for producing a filtered signal having a given frequency and a radio transmitter transmitting at frequency set by a variable frequency oscillator.

7.598.815 Multiple Frequency Generator for Quadrature Amplitude Modulated communications.

7.577.225 Digital phase-locked loop.

7.733.143Duty cycle correction circuit for high-speed clock signals.

7.808.329Methods and apparatus for an improved phase linearity in a multi-phase based clock/timing recovery system.

1. J. Chen, F.Saibi, E. Sackinger, J. Othmer, F. Yang, J. Lin, T. Huang, TP Liu, K. Azadet “A Multi-Carrier QAM Transceiver for Ultra-Wideband Optical Communication” IEEE Journal of Solid-State Circuits, vol 41, pp1876-1893, Aug 2006.

2. J. Chen, F.Saibi, E. Sackinger, J. Othmer, F. Yang, J. Lin, T. Huang, TP Liu, K. Azadet “An integrated CMOS transceiver for a 40Gb/s SCM optical communication system” IEEE 2005 Custom Integrated Circuits Conference (CICC), pp135-138, San Jose, California, Sept. 18-21, 2005.

3. J. Chen, G. Sheets, C. Guo, F. Saibi, F. Yang, K. Azadet “Electrical backplane equalization using programmable analog zeros and folded active inductors” 48th IEEE Midwest Symposium on Circuits and Systems, pp. 1366-1369, Cincinnati, Ohio, August 7-10, 2005.

4. Yang F., O'Neill, J.H. Inglis, D., Othmer, J. “A CMOS Low-Power Multiple 2.5-3.125Gb/s Serial Link Macrocell for High IO Bandwidth Network ICs” IEEE Journal of Solid-State Circuits, Vol.37, No.12, Dec. 2002.

5. F. Yang, J. O'Neill, P. Larsson “A 1.5V 86mW/ch 8-channel 622-3125Mb/s Serdes with selectable mux/demux ratio”, IEEE International Solid-State Circuits Conference (ISSCC) 2002, San Francisco, USA.

6. F. Yang, C.C. Enz “A low distortion BiCMOS 7th-order Bessel filter operating at 2.5V”, IEEE Journal of Solid-State Circuits, vol.31, pp321-330, Mar. 1996.

7. F. Yang, C.C. Enz “Design of low-power low voltage log-domain filter” IEEE International Symposium on Circuits & Systems(ISCAS) 1996, Atlanta, US.

8. F. Yang, C.C. Enz “ A 2.5V low distortion 7th-order Bessel Filter” IEEE Custom Integrated Circuits Conference(CICC)1995, Santa Clara, US.

9. F. Yang, C.C. Enz “A low-voltage low distortion BiCMOS OTA for CT filters” IEEE International Symposium on Circuits & Systems (ISCAS) 1995, Seattle, USA.